The present invention relates to a semiconductor package and semiconductor module and, more specifically, to a semiconductor package and semiconductor module wherein optical interconnection technology is applied for input/output of signals.
In recent years, as the integration density and operation speed of semiconductor chips increase, higher densities are required for mounting and interconnection for semiconductor packages.
One known way to achieve such requirements, as disclosed for example in Japanese Unexamined Patent Publication No.62-73651, is to use a technology called silicon-on-silicon packaging in which semiconductor chips are mounted by flip-chip bonding on a wiring substrate made of a semiconductor wafer. In this mounting technology, high-density interconnections can be formed on the wiring substrate by a process similar to that which is used for forming interconnections on semiconductor chips, thus resulting in a higher assembling density than in the case where semiconductor chips are separately mounted in individual packages. Furthermore, a high density of interconnection also results from another feature of this technology that semiconductor chips are connected to the wiring substrate via solder bumps.
However, the above technology has a limitation in the number of input/output pins available for a package base. Input/output pins of a wiring substrate are connected to a package base by means of wire bonding or TAB (tape-automated bonding) performed in a peripheral region of the wiring substrate, or by means of a feedthrough formed to extend through the wiring substrate. As a result, the number of input/output pins available for a package base is limited by pitches of the bonding and input/output pins themselves.
As described on pages 285-287 of "Bear Chip Mounting using COB and TAB-Recent Technology Development and Means for Improving Reliability-(1990)" published by Gijutsu Joho Kyokai (Association for Technical Information), the pitches of bonding wires and TAB are limited by the reliability of bonding portions. The possible minimum pitches are approximately 150 .mu.m and 80 .mu.m for wire bonding and TAB, respectively. Furthermore, because connections using wire bonding or TAB are performed in a peripheral region of a wiring substrate, it is difficult to obtain a short length of signal interconnection. This, in turn, results in a problem that there is a large delay for signals to propagate from chips to the peripheral region of the wiring substrate where bonding wires or TAB leads are connected to the substrate.
On the other hand, feedthroughs are formed in a wiring substrate by thermo-migration or anisotropic etching, as described, for example, in Japanese Unexamined Patent Publication No.62-73651. The pitch of feed-throughs is limited depending on the thickness of a wiring substrate. In the case of feedthroughs, a pitch of a few hundred .mu.m is available. However, for electrical insulation between feedthroughs, additional insulating films are needed, or a special voltage supply is required. For this reason, this technology is not in common use yet.
As described, for example, in Proceedings of 41th Electronic Components & Technology Conference (1991), pp. 234-244, the pitch of input/output pins on a package base is limited by structure and electrical characteristics of the pins on the package base and of connectors formed on a wiring substrate. For example, a special spring mechanism is required in connectors formed on a wiring substrate so as to contact pins with connectors, and a special mechanism is required so as to reduce the force needed for inserting pins. Thus, serious mechanical limitations exist in reduction in the size of pins or connectors. On the other hand, if the pin pitch is reduced too much, an increase will occur in crosstalk or in inductance. Thus, there are electrical limitations especially in applications where high speed signals are input or output. Due to the above problems, the lower limitation of input/output pitches is about 2 mm for the case of centered lattice arrangement.
In the reference cited above, it is proposed to use spring type connectors having a special form or connectors similar to TAB structure instead of input/output pins. In the case of connectors of such a spring type, it is possible to make pitches as small as 1 mm. However, high mechanical strength and high reliability comparable to those of conventional input/output pins have not been established yet. Therefore, this type of connector is not in common use yet. In the case of the TAB type connector, interconnection is also performed from the peripheral region of a package base to the outside as in the conventional TAB and, thus, there exists a problem of large signal propagation delay across the package base.
To increase the number of input/output pins is one of the important issues for semiconductor packages. Especially in order to construct a large scale information processing system with a large number of high-assembly-density packages, it is required to make interconnections among these packages by a large number of wires.
Let us take as an example a silicon-on-silicon package having several instruction processor chips and a system control circuit chip mounted on it. When N packages of this kind are used for constructing a multi-processor system, an interconnection network among N semiconductor packages (that is, among system control circuit chips) is a key which will determine the system performance. In order to achieve the highest performance, a perfect interconnection network is desirable. Because the number of interconnection wires in a perfect interconnection network is proportional to N(N-1), a huge number of interconnection wires would be required to realize such a system. For example, when N is equal to 8 and, furthermore, if 64-byte connection is assumed, then the total number of interconnection wires will be as large as 57,000, which implies that about 7,000 input/output pins will be required for each package. If we can assume that a reasonable package size is of the order of a few inches square, then the maximum possible number of input/output pins is limited by various problems described above, and is about a few thousand. Therefore, the conventional technology cannot realize a perfect connection network which is ideal for such a system.
We discussed above an example of a multiprocessor system. When the conventional technology is used in other information processing systems such as a super parallel processor or a large scale exchange system, there are also similar problems. That is, the performance of these systems is limited by the limitation of the number of input/output pins of semiconductor packages.
Optical interconnection is regarded as one of the promising technologies for solving the above bottleneck with regard to input/output pins. In general, it is considered that the optical interconnection technology provides various advantages over the conventional electrical interconnection, that is, it is quite free from crosstalk, ground noise, and signal wave degradation. Furthermore, it can provide high speed and broad band transmission. These advantages lead to higher density of interconnection compared with the conventional electrical technology. For example, Japanese Unexamined Patent Publication No.63-502315 discloses one such optical technology, in which semiconductor chips and optical devices are mounted on stacked wafers and interconnection between different wafers is achieved by light passing through wafers.
However, in this technology, nothing is taken into consideration about a way for supplying electrical power to semiconductor wafers, about relationships with regard to location between a semiconductor wafer and optical devices, about cooling means in a package for cooling semiconductor chips, and about an input/output means for optical signals from or to a package. Therefore, the conventional optical interconnection cannot be simply applied as a means to solve the bottleneck with regard to input/output pins of semiconductor packages.
When optical devices are mounted by flip-chip bonding on a semiconductor wafer, the flip-chip bonding leads to a reduction in the density of semiconductor chips on a semiconductor wafer because of the area for optical devices. On the other hand, there is a serious difficulty in a process to form optical devices monolithically on a semiconductor wafer. Besides, because of the difference in thermal expansion coefficient between optical devices and a semiconductor wafer, degradation often occurs in optical devices. Furthermore, because a high speed and/or very large scale semiconductor chip generates a large amount of heat, a package must be provided with some cooling means on its lid as described in Japanese Unexamined Patent Publication No.62-73651. When optical signals are input or output through side faces of the package, additional space around the package is needed for optical inputs and outputs so as to avoid obstruction to effective cooling, as described for example in Japanese Unexamined Patent Publication No.63-237486. This, in turn, leads to another problem of a reduction in assembly density of packages mounted on a circuit board. If these facts are considered, it is desirable to realize optical means for signal input and output through a package base.
One known technology for input/output of optical signals performed via a package base is an optical package as described in Japanese Unexamined Patent Publication No.64-30274. In this technology, optical fibers are fixed into through-holes formed in a package base, and optical devices are mounted by flip-chip bonding on the locations facing to the end surfaces of optical fibers. However, this technology cannot be applied directly to semiconductor packages because of the lack of enough consideration on the location of optical devices, treatment of optical fibers, and cooling of optical devices. When optical devices as well as semiconductor chips are mounted by flip-chip bonding on a wiring substrate, a problem occurs that the assembly density of semiconductor chips decreases. Besides, because optical fibers are always fixed to the package base, an inconvenience occurs in treatment of optical fibers or in insertion and/or removal of input/output pins. Furthermore, because optical devices for high speed transmission such as semiconductor lasers exhibit strong dependence on temperature, adequate cooling is required.
As described above, in order to apply optical interconnection technology to high speed and/or high density semiconductor packages, overall consideration should be given not only to input/output means for optical signals from and to packages, but also to assembly density of semiconductor chips, arrangement of optical devices, cooling means for semiconductor chips and optical devices, assembly density of packages on a circuit board, and treatment of input/output pins and optical fibers.